1. Field of the Invention
The present invention relates to an SMPS (Switching Mode Power Supply) circuit for a Plasma Display Panel (hereinafter, referred to as ‘PDP’); and, more particularly, to an SMPS circuit capable of reducing the total size and volume of a PDP power system by driving a plurality of DC/DC converters for supplying high sustain voltage and address voltage and a plurality of low voltages with one transformer and capable of improving power conversion efficiency and reliability by using a clamp circuit.
2. Description of the Related Art
Generally, a PDP as a flat panel display device using a penning gas in a discharge phenomenon is a display device using a luminescent phenomenon caused by discharge generated between narrow electrodes coated with a dielectric by using a Ne or He gas, or the like of a relatively high pressure as a base gas.
The PDP is thinner and lighter than a CRT (Cathode-Ray Tube) which has been principally used as a display means and has an advantage to realize a large screen with high definition. Further, the PDP includes a plurality of DC/DC converters generating various voltages for supplying high voltages (Vs, Va, Vset, Vscan and so on) for plasma discharge and supplying a plurality of low voltages to an image processing unit, a fan, an audio, and so on.
FIG. 1 is a block diagram showing an example of a conventional PDP power system. As shown in FIG. 1, the conventional PDP power system is inputted with 90˜270Vrms from a commercial line input source 1 and set-up or boosted-up through a PFC (Power Factor Correction) 2 for avoiding harmonic wave regulation to output a DC voltage of approximately 370˜400 VDC and supply various powers needed in PDP driving through a plurality of DC/DC converters from the outputted DC voltage.
First of all, the PFC 2 for performing improvement of power factor is positioned on the most front stage of the SMPS for PDP and mainly adopts Boost topology representing an excellent characteristic in a PFC performance.
The output voltage of the PFC 2 is inputted to a plurality of DC/DC converters 3˜7 for supplying high voltage of sustain driving power and address power and to a DC/DC converter 8 for supplying a plurality of low voltages. At this time, the output of Vs 3 power is used as the sustain driving power and inputted to a scan voltage (VSCAN) 4 and reset voltages (VSET and VE) 5 and 6. The voltages outputted from the DC/DC converters are inputted to a PDP driving module 9 to drive a PDP device.
Meanwhile, in FIG. 1, a plurality of low voltage elements supplied with the low voltages by the DC/DC converter 8 for supplying the low voltages are represented by one Multi 10.
FIG. 2 is a graph showing a power on sequence of a conventional PDP power system.
As shown in FIG. 2, powers should be applied according to the sequence shown in FIG. 2 and the reason is as follows.
Generally, a PDP power system is characterized by a high voltage and a low current and therefore is considerably influenced by switching loss rather than conduction loss.
Further, because a very large surge current flows in the PDP in case of discharge according to a luminescence principle, a plurality of large capacitors should be added to a power and driving board in parallel in case of the sustain voltage and the address voltage and because a driving module of the PDP supplies a lot of electrodes with powers needed for each of the electrodes by high-speed switching, the PDP is mostly composed of switching elements using semiconductors.
Therefore, in order to protect the switching elements and prevent anomalous discharge from being generated in case of primary power application, the powers should be applied according to the sequence as shown in FIG. 2.
Accordingly, in recent, the powers are generally applied in sequence of a low voltage system (for signal processing and driving) Vcc, an address system Va and a sustain system VS and the powers are reversely removed.
FIG. 3 is a circuit diagram of a conventional SMPS circuit for PDP. As shown in FIG. 3, the SMS circuit includes a plurality of DC/DC converters 31˜34 for supplying a sustain voltage Vs, an address voltage Va, a plurality of low voltages VM, and a standby voltage STD_BY. At this time, the standby voltage STD_BY is a driving voltage for driving elements of the SMPS circuit for PDP.
The DC/DC converters 31˜34 are insulating type converters using three transformers T1, T2 and T3 for electric insulation between input and output. At this time, a DC/DC converter 31 for supplying the sustain voltage VS is a half-bridge converter, DC/DC converters 32 and 34 for supplying the address voltage Va and the standby voltage STD_BY are flyback converters, and a DC/DC converter 33 for supplying the low voltages VM is a buck-converter as a step-down type converter.
At this time, because voltage stress applied to switching elements QA and QM has the same size as that of input voltage and each switch driving waveform has a half-wave symmetry shape, the half-bridge converter 31 is widely utilized as a structure suitable for a high-capacity converter, wherein the switching elements are controlled through a controller in a Pulse Width Modulation (hereinafter, referred to as ‘PMW’) or Pulse Frequency Modulation (hereinafter, referred to as ‘PFM’) method.
Further, the flyback converters 32 and 34 of which inputs and outputs are insulated are most frequently used as a circuit having the smallest number of components and the buck-converter 33 is a DC to DC converter realized by stepping-down an input voltage to obtain an output voltage with a desired voltage, wherein the output voltage is lower than the input voltage.
Referring to FIG. 3, hereinafter, an operation principle is briefly described. First of all, after diving an input voltage of a PFC by using a capacitor (Clink), two switching devices QA and QM with an operation duty ratio or an operation frequency adjusted by a controller are alternately switched, an AC voltage of a square waveform is transmitted to a secondary side of a transformer T1, the transmitted AC voltage is rectified through a plurality of half-bridge type diodes, and then the rectified AC voltage is smoothed by a capacitor CO to obtain a DC voltage VS and stabilize an output voltage VS with a feedback circuit.
At this time, a linear regulator outputting a driving voltage Vg by receiving the low voltage VM outputs a gate voltage Vg of the switching element included in the PDP driving module (not shown) with a predetermined size always.
And, a high power MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) is mainly used as a switching device in the conventional SMPS circuit. The above-mentioned operation principle is related to the half-bridge 31, however, the operation principle of the flyback converters 32 and 34 are almost the same.
However, the conventional SMPS circuit for PDP has advantages that the transformers T1 and T2 are required for each of the DC/DC converters for supplying the sustain voltage VS and the address voltage Va and thus a space occupied by components is enlarged to increase the size and volume of the PDP power system over all, thereby increasing a manufacturing cost.
Meanwhile, FIG. 4 is a graph showing a load characteristic of a sustain voltage output stage and an address voltage output stage according to a conventional PDP driving manner. As shown in FIG. 4A and FIG. 4B, the load of the sustain voltage output stage and the address voltage output stage has a complicated load characteristic to repeat overload from no-load at a period of 16.67 ms.
But, as shown in FIG. 4C, the sum of the load characteristic of each of the stages in case of PDP operation is nearly uniform and when using such a characteristic, it is possible to facilitate optimal voltage control of a PDP power and improve power conversion efficiency and reliability since there is little change of the operation frequency or the operation duty ratio.
However, the conventional SMPS circuit for PDP has a disadvantage that it is not possible to use such a characteristic as shown in FIG. 4C by using the transformers for each of the DC/DC converters for supplying the sustain voltage VS and the address voltage Va, and therefore the optimal voltage control of the PDP power is difficult and the change of the operation frequency or the operation duty ratio is extreme to reduce the power conversion efficiency and the reliability.